1. Technical Field
The present invention relates to electronic structures and methods for fabrication and more particularly to devices and methods which electrically characterize process variations due to mask misalignment.
2. Description of the Related Art
As device size shrinks aggressively in advanced very large scale integration (VLSI) technology, increased process variation causes devices to behave differently from intended operation. For example, the post-fabrication terminal current, at certain terminal voltages, for a device may differ from desired current.
One significant cause of variability is non-rectangular fabrication of a device's gate (PC) and active diffusion (RX) regions. This non-rectangularity emerges from extremely shrunk device sizes and imperfect lithographic processes. A device's region of interest (ROI) is the PC overlap of an RX region. Several fabrication mask optimization techniques such as Optical Proximity Correction (OPC) and Resolution Enhancement Techniques (RET) have been developed and aggressively optimized to achieve near rectangular ROI. PC and RX regions are formed at during fabrication steps. A lithography tool has to physically pick a mask for the formation of each region. This can result in overlay error in mask alignment on a wafer. This overlay error is becoming closer in magnitude to smallest relevant dimensions on a wafer such as PC pitch (distance between two PCs). Hence, maintaining a rectangular ROI is becoming an increasingly difficult task.
Overlay variation due to fabrication tools while aligning a mask with a wafer and patterning occurs between different layers (PC-RX, RX-CA, PC-CA, etc.). For example, the impact of PC-RX overlay results in variations in device width and induced overlay with other critical layers (e.g., contacts layers (CA)). The impact of PC-CA or RX-CA overlay includes hard defects and increased resistance/capacitance. PC-RX-CA overlay is a growing concern with reduced device widths (RX), and reduced PC pitch in static random access memory (SRAM) cells and other structures.
FIG. 1 illustrates a device 10 with non-rectangular ROI due to misalignment between PC and RX masks. As shown in FIG. 1, misalignment 15, 17 between PC and RX layers can affect the device characteristics by modifying the device width resulting in variability in circuit functionality, varying distance between PC and contacts (CA) which introduces variation in parasitic resistance and capacitances, varying CA overlap of RX which introduces variation in contact resistance, and causing hard defects (e.g., PC to CA shorts).
A current practice is to fabricate some pattern at every different mask level and measure the distance between every pair of patterns. Any deviation in the distance from the designed distance is the measure of overlay error. These measurements are made typically using optical metrology tools, such as a Scanning Electron Microscope. This optical measurement technique is very time consuming. As a result, practical implementations are limited to only a few measurements per wafer. Also, the optical measurement, does not allow for any adaptive self-repair schemes in the electrical circuit.
Traditional measurements are often supplemented by measuring current-voltage characteristics of several devices to measure variability. Measurements using the traditional approaches include the electrical variability due to all the sources of local and global process variations. Local sources include threshold voltage and current variations due to random dopant fluctuations, PC line-edge roughness, etc. Global sources include lithographic variations such as variation in focus, dose, etc. in PC/RX as well as etch variations. It becomes extremely difficult to isolate the variations due to overlay alone, to qualify the fabrication tool and to characterize the technology.